A counterfeited electronic part is one whose identity has been deliberately misrepresented.

Identity of electronic part includes:

• Manufacturer
• Part number
• Date and lot code
• Reliability Level
• Inspection/Testing
• Documentation

External Visual Inspections - External Visual inspection is to detect validity of logo, part number, lot code, date code, and /or PB-free marking; marking technique; quality of marking; mold cavities; straightness, coplanarity, scratches, bridging or other defects in terminations; surface texture.

Heated Chemical Test is performed on electronic parts for secondary coding. The process is done by heating the components to a certain temperature then submerging into a chemical. After the process is completed, a picture of the device is takeng under a microscope to show the secondary coating, if it is has one.

Pin Correlation testing/Curve Trace Analysis is used to confirm that random or full sampling of the parts in a lot are functioning with the same tolerance in respect to the date sheet or known good device. This test combined with decapsulation and X-Ray, this is highly effective method of detecting sub-par components.

The objective of electrical testing is to determine the quality of each product to avoid counterfeit distribution and production. This test is accomplished by running a suite of tests or as many vital tests as possible to check the DC, AC, functional and parametric performance of the component in question. The intricacies of these tests can easily give test engineers a robust data set that they can use to uncover a counterfeit component where other test methodologies fail to uncover any problems or anomalies. 

According to industry statistics, it is recommended to test at minimum 10% of the lot. These will give a very good understanding of fallout percentage

Bake-out conditions (time and temperature) for SMT parts should be provided by the part manufacturer.  However, in most cases manufacturers specify the industry standard bake: 125 °C for 24 hours [1].  Obviously this condition cannot be optimal for all cases.  For example, if deterioration of solderability and lead finishing at high temperatures is a concern, the maximum allowable temperature must be decreased (sometimes temperatures as low as 40 °C are recommended).  The bake-out times depend on the size and shape of the package; however, in most cases these factors are neglected.  One may use the bake-out regimens recommended by IPC standard (IPC-TM-650): 125 °C for 6 hours for packages with less than 2 mm of body thickness, and 24 hours for thicker packages.